Underfill selection for large body (50×50mm) lidded flip chip BGA package with ELK 40nm Pb-free bumps

Flip chip has become the preferred package solution for high performance IC and microprocessor device [1]. In the area of flip chip, advanced Si node is always the mainstream technology. The integration of highly fragile ELK inner layer dielectric (ILD) material plays an important role to reduce the circuit delay time. In addition, the increasing performance demand continues to drive the scaling of feature size of the silicon as well as tighter bump pitch, smaller bump diameter and large die size for future flip chip packages [2]. From the last decade, there has been a significant focus on the development of Pb-free bump interconnection in flip chip package [3]. The Pb-free bump interconnection leads to significant challenges because the elastic modulus and yield strength of Pb-free alloys are significantly higher than that of conventional eutectic Sn-Pb material, and higher melting temperature is required to meet the Pb-free soldering in chip attach process. As a result, ILD delamination has emerged as a major reliability concern with the adoption of the intrinsically higher stiffuess of Pb-free solder and lower mechanical strength of ELK dielectric materials in silicon backend structure. It is a challenge to manufacture a robust and reliable advanced flip chip product [4-6]. In this paper, we summarize some of the early development work of the high performance ASIC. The die size of the test vehicle is approximately 18x19mm fabricated using 40nm ELK technology incorporating Sn-1.8Ag plated bumps whose pitch is 150um (minimum). It is fabricated on 300mm wafer with polyimide passivation. The laminate is a 50x50mm square substrate with 800um core and 5-2-5 (12 layers) build-up structure. The Pb-free BGA has 2397 pads with 1.0mm pitch and full array format. It is well known that underfill materials and related processes are key technology for flip chip BGA (FCBGA) packaging. Underfill is an epoxy silica composite material with optimum thermo-mechanical properties (CTE, Tg, Modulus) to minimize stress transfer to die, then to prevent solder joint fatigue, ELK ILD delamination and die crack. In this study, UF selection is conducted to compare different underfill materials process capability, compatibility and reliability performance in accelerated stress tests. Common failure modes are studied, e.g., ILD delamination besides UF crack and interfacial delamination between polyimide and UF. One underfill option has passed internal qualification test including uHAST 96hrs, TCB 1000 cycles and HTST 1000hrs.