A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm

This paper presents a wide-operating-range, all digital delay-locked loop (ADDLL) that possesses fast and anti-harmonic lock behavior using a novel fast-lock variable SAR (FVSAR) algorithm. The FVSAR algorithm provides an efficient search sequence for the length-control code of the delay line in the ADDLL. An 11-bit FVSAR ADDLL prototype was fabricated in the TSMC 0.18-μm CMOS process. The chip's core area is 0.2 mm
²
. With 1.6-V supply, the power consumption of the ADDLL chip is less than 10 mW. Compared with the conventional VSAR algorithm, the proposed FVSAR ADDLL reduces the lock time by at least 35% when the input clock frequency is between 66 MHz and 550 MHz.