Resource efficient and area optimized Gr⊘stl implementation on FPGA

SHA-3 is the next family of cryptographic hash algorithms. The purpose to develop SHA-3 is to remove the vulnerabilities of SHA-1 and SHA-2. This paper implements Grostl hash algorithm on FPGA, which was among the five finalists of the competition. This work focuses on low area implementation of Grostl for optimum throughput to area ratio (TPA). For this purpose fully autonomous interleaved design architecture is used. Interleaved design executes permutations P and Q serially one after another. Interleaved design is implemented with two approaches one using Distributed Memory and the other using Block Memory. The post place and route results obtained on virtex-6 are throughput 6844Mbits/s, occupied slices 1470 and TPA 4.65.