Implementation of Convolutional codes on FPGA

There is always a desire for error free communication, so the Convolutional Encoding with Viterbi Decoding is a step towards an error free communication. In this paper, Convolutional Encoder with Viterbi Decoder is applied on Basys2 Sparten-3E Field-Programmable gate array (FPGA) Board. In this paper, there are two parts. In first part, bit error rate performance is shown by mean of simulations on different channels. Second part is hardware based, in which all these simulations are implemented on FPGA. This paper also includes real time performance of Convolutional codes and presents the convolutional encoder with coder rate 1/3.