On the impact of the layout of MOSFET test-structures on NBTI-, PBTI- and HCS-lifetime due to PID

We introduce and discuss in our paper an alternative to protection diodes and compare it with different sizes and placements of diodes. In contrast to other PID publications we do not focus on the PID itself but on the impact on full transistor-lifetime estimations. We evaluate long-term NBTI, PBTI and HCS experiments.