A logic 2T gain cell eDRAM with enhanced retention and fast write scheme

A logic-process embedded DRAM with 2T multi-Vth PMOS gain cell with one high-Vth for retention enhancement and one low-Vth transistors for fast read speed is proposed. To improve the write speed, the write back step and sense step are separated, and the write before sense schemes are adopted to improve write speed and suppress the noise disturbance to adjacent bitlines. The simulation results illustrate that the write cycle of memory is 3ns which corresponding to 333MHz operating frequency. The cell size is 64F
²
and is 40% of SRAM in the same process generation.