Multi-mode timing closure of D6000 Collective Communication Chip

This paper describes the design for multi-mode timing closure of a Collective Communication Chip in Dawn 6000. As the introduction of DFT in this chip, multiple test modes have been brought in. Therefore, how to achieve multi-mode timing closure of such a complex chip becomes a challenge to us. To manage the DFT test modes flexibly and also reduce test cost, the traditional IEEE 1149.1
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compliant TAP, known as JTAG, is exploited, however whose timing closure also shares us a lot of concern. Facing so many timing closure relative challenges, many specific techniques have been implemented in the chip, such as a customized clock control scheme, accurate timing constraint and a novel timing closure method. Finally, the one-pass tape-out has proven that our design works as expected.