Selective parallel CRC computation schemes for RapidIO

RapidIO is a high-performance standard for embedded interconnections. Due to different ending alignments of RapidIO packets, the corresponding CRC computations should be adjustable. In this paper, two selective parallel computation schemes based on simplified intermediate value equations are proposed. Compared with the reference designs, the power dissipations can be reduced by more than 30% meanwhile better balances between the speeds and resource consumptions can be achieved.