A study on gate-AU-around (GAA) polycrystalline silicon channel SONOS flash memory

In this study, the gate-all-around (GAA) poly-Si channel flash memories with charge trap layer (Si
₃
N
₄
) have been successfully fabricated. Electric characteristics of fabricated devices including threshold voltage shift with program/erase operation have been investigated. Gate configurations were structured differently according to each defined channel width. Results show that devices with gate-all-around structure have superior program efficiency. To investigate the effect of gate configuration on the program efficiency, TCAD simulation was carried out.