A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver

This paper presents a new topology of a PMOS based LVDS voltage-mode output driver. This topology is designed to meet the requirements of low power consumption and high data rates applications. The driver, which consists of a pre-driver stage and an output stage, uses a positive feedback technique at the output stage to achieve line impedance matching and power saving. The pre-driver stage is used to set the driver's swing and common mode output voltage. The pre-driver and the output stage consume only 9mW of power at 3 Gbps speed while operating from a 1.8V voltage supply. The system is designed and simulated using CMOS 180nm technology and is fully compliant with LVDS output swing and common mode voltage specifications.