A low-power fully differential cyclic 9-bit ADC

This paper describes a low-power fully differential cyclic ADC. It utilizes a 4-bit binary weighted capacitor array to obtain 9-bit resolution. The operational amplifier with the slew rate detection is used to increase the speed of the ADC. The simulated power consumption of the ADC is 7.4 μW@1.4 V at the sampling rate of 10 kS/s. The simulated DNL and INL are 0.1/-0.18 LSB and 0.22/-0.2 LSB respectively. The results are based on post-layout simulations.