Real-time FPGA connected component labeling system

The implementation of a connected component labeling algorithm (CCL) for real-time operation is presented in this paper. The algorithm, which was designed and implemented following a model-based methodology centered on Matlab/Simulink and Xilinx-System Generator, uses horizontal and vertical blanking periods to improve the quality of labeling and increase the operation speed. Its performance, with a VGA 640 × 480 P @ 60 Hz video, is shown by means of its integration on a complete video processing system over a Spartan-3A DSP 3400 development board.