High-throughput FPGA-based emulator for structured LDPC codes

FPGA-based emulators are used to evaluate the LDPC codes performance at low bit error rates (BER). We propose an emulator for structured LDPC codes that takes advantage of the early termination in high signal-to-noise ratios (SNRs), where most of the received frames can be decoded in one iteration. Moreover, the data generation (received frames) was parallelised to avoid bottlenecks when the decoder throughput is maximum. The emulator was implemented on a Virtex-6 device a (2048,1723) RS-Based LDPC code using the normalised-MS algorithm, achieving an average throughput of 1.35 Gbps with a single core and, 5.7 Gbps with 4 cores in a single FPGA device. The achieved throughput is 4 times faster than the state-of-the-art FPGA emulators in the literature.