A dual threshold voltage technique for glitch minimization

We propose to use dual-threshold voltage (dual-V
_th
) assignment for glitch reduction. We present a heuristic algorithm address this problem. Experimental results on 6 ISCAS85 benchmark circuits implemented in a 65 nm industrial low power CMOS process report more than 16% of glitch reduction on average, and up to 41% for C432 benchmark circuit. To further minimize glitches, we propose to unify gate-sizing and dual-V
_th
techniques into a single optimization process. Results show an improvement of 10% on average compared to the conventional gate-sizing method. Spice simulations of C432 benchmark circuit report more than 27% and 48% total energy reduction by means the proposed dual-V
_th
and dual-V
_th
/gate-sizing algorithm, respectively.