Design and Implementation of a DDR3-based Memory Controller

Memory performance has become the major bottleneck to improve the overall performance of the computer system. DDR3 SDRAM is a new generation of memory technology standard introduced by JEDEC, support multibank in parallel and open-page technology. On the basis of in-depth study of DDR3 timing specification, design a DDR3-based memory controller. Memory access control module is the most key component of the memory controller. Using the stream test bench evaluate the performance, experimental results show that the memory controller of our design can correctly schedule memory access transaction, improve memory bandwidth.