Poly-phase sigma-delta modulation

A new circuit is described for the implementation of analog sigma-delta modulation. It is based upon the use of a poly-phase sampler with the aim of obtaining high over-sampling ratios at low clock frequencies. A detailed analysis of second-order systems is made to predict its performance. The basic modeling comprises the incorporation of sampling noise within limit cycle oscillations of the modulator. It is shown that the polyphase sigma-delta modulator can be conceived as an internally sampled asynchronous sigma-delta modulator. The theoretical model presupposes a low limit cycle frequency as compared with the effective sampling frequency. In spite of the fact that this condition is not met in the extreme of conventional single-phase sigma-delta modulation, the theoretical result obtained for this special case is close to the result obtained from the conventional sampled data model. Poly-phase sigma-delta modulation may therefore be regarded as a generalization of conventional single-phase sigma-delta modulation. The results of the theory are illustrated by simulation results of a practical design example.