Clock cycle oriented data bandwidth aware merge mode motion vector selection algorithm for HEVC

The latest video coding standard called high efficient video coding (HEVC) has been standardized recently to provide higher coding performance than previous state-of-the-art video coding standard H264/AVC. However, the near 50% bitrate reduction compared to H.264/AVC mainly comes from the adoption of several advanced coding techniques but at the expense of increased coding complexity as well as hardware design difficulty. In addition, the system bus uncertainty caused by multiple system module accesses also noticeably determinates the overall system throughput. Therefore, this paper proposes a clock cycle oriented data bandwidth aware merge mode motion vector selection algorithm for HEVC. In this paper, the merge mode motion vector candidates are first prioritized for guiding the upcoming motion vector candidate selection process. Afterward, the clock cycles during video coding system operation are considered to evaluate the current data bandwidth condition, and the current data bandwidth condition is adopted to decide the prioritized merge mode motion vector candidate. Simulation results demonstrate that our proposed algorithm can achieve higher throughput requirement with ignorable rate distortion performance degradation.