DDR3 SDRAM memory interface design for com module

Increases in speed and capacity, and decreases in area size and power consumption of computer memories are key guidelines in DRAM technology development. Another important requirement is improvement of memory-memory controler interface. Due to the increase in clock frequency, it is necessary to pay attention to the signal integrity. Successful interface design requires a large number of simulations. After the design phase is over, it is necessary to verify the interface to prove that the circuitry functions according to the design specifications. This paper provides a primer on DDR3 SDRAM memory interface design for COM module. The complete process is described, from schematics to preliminary simulations, to printed circuit board design, and verification. This is an example of embedded system design.