Topological and Central Trigger Processor for 2014 LHC luminosities

The ATLAS experiment is located at the European Center for Nuclear Research (CERN) in Switzerland. It is designed to observe collisions at the Large Hadron Collider (LHC): the world's largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider upgrade. During 2011, the LHC reached instantaneous luminosities of 4 × 10
³³
cm
^-1
s
^-1
and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the nominal 40MHz collision rate to a manageable event storage rate up to 400Hz and, at the same time, select those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5μs. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP) and by 2014 a complete new electronics module: the Topological Processor (TP). The TP will make it possible, for the first time, to concentrate detailed information from sub-detectors in a single Level-1 module. This allows the determination of angles between jets and/or leptons, or even more complex observables such as muon isolation or invariant mass. This requires to receive on a single module a total bandwidth of about 1Tb/s and process the data within less than 100 ns. In order to accept this new information from the TP, the CTP will be upgraded to process double the number of trigger inputs and logical combinations of these trigger inputs. These upgrades also address the growing needs of the complete Level-1 trigger system as LHC luminosity increases. During the LHC shutdown in 2013, the TP and the upgraded CTP will be installed. We present the justification for such an upgrade, the proposed upgrade to the CTP, and tests on the TP demonstrator and prototype, emphasizing the characterization of the high speed links and tests of the topological algorithm's latency and logic utilization.