1V supply 16-bit second order Sigma-Delta modulator in a 90nm CMOS process

This paper presents a second order Sigma-Delta modulator using a 1V dual supply in 90nm technology. The schematic modulator design achieves a signal-to-noise ratio (SNR) of 96.7 dB or 15.7 bits. A gain boosted fully differential folded cascode operational transconductance amplifier (OTA) with a switched capacitor common-mode feedback circuit is implemented as the integrator. The OTA design is able to achieve a 500 V/V DC gain, with a 400mV output swing, Gain Bandwidth (GBW) of 303.5 MHz and a phase margin of 50.9 degrees. A fully-differential preamplifier-based latched comparator is also implemented, achieving a rail-to-rail output and a sensitivity of 10 µV. Data presented from each of the blocks are from post-layout simulations.