Loading [a11y]/accessibility-menu.js
A template-based methodology for efficient microprocessor and FPGA accelerator co-design | IEEE Conference Publication | IEEE Xplore

A template-based methodology for efficient microprocessor and FPGA accelerator co-design


Abstract:

Embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration fo...Show More

Abstract:

Embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration for SW/HW designs is a very time consuming task, while the adhoc approaches and the use of partially automatic tools usually lead to less efficient designs. To support a more efficient codesign process for FPGA platforms we propose a systematic methodology to map an application to SW/HW platform with a custom HW accelerator and a microprocessor core. The methodology mapping steps are expressed through parametric templates for the SW/HW Communication Organization, the Foreground (FG) Memory Management and the Data Path (DP) Mapping. Several performance-area tradeoff design Pareto points are produced by instantiating the templates. A real-time bioimaging application is mapped on a FPGA to evaluate the gains of our approach, i.e. 44,8% on performance compared with pure SW designs and 58% on area compared with pure HW designs.
Date of Conference: 16-19 July 2012
Date Added to IEEE Xplore: 10 January 2013
ISBN Information:
Conference Location: Samos, Greece

References

References is not available for this document.