The application of novel failure analysis techniques for advanced multi-layered CMOS devices

The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection. Without these tools, FA on extremely complex devices such as microprocessors will be extremely difficult, if not impossible.