Silicon tunneling field-effect transistors with tunneling in line with the gate field

We present experimental results on the fabrication and characterization of vertical Si tunneling field-effect transistors (TFETs) in a device geometry with tunneling in line with the gate field. Compared to vertical Si TFETs without this geometry modification, on-currents are increased by more than one order of magnitude with
I
_ON
= 1.1 μA/μm at
V
_DS
= 0.5 V and an
I
_ON
/
I
_OFF
ratio of 3.4 ·10
⁴
in n-channel operation. We present further suggestions for device improvements.