Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track

Summary form only given. Recent advances in semiconductor process technology especially interconnects using Through-Silicon Vias (TSVs) enable heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and then stacked together to form a system. Compared to conventional wire-bond chip interconnections, TSVs offer several advantages such as high density, low latency, low power, and possibly lower cost. TSVs provide vertical interconnects and hence naturally used for 3D vertical stacking of multiple dies, However, TSVs also have attractive benefits in interconnecting dies, which are placed next to each other on top of a passive silicon interposer. TSMC has proposed CoWoS (Chip-on-Wafer-on-Substrate) process as the standard design paradigm to assemble interposer-based 3D ICs. Figure 1 shows an example of a CoWoS design with three heterogeneous (RF, logic and memory) dies. In order to reach quality requirements for volume production, several challenges need to be resolved for 3D ICs. Many of these challenges open up new horizon for the EDA industry and academia as they require innovative and compute efficient approaches. One of the critical challenges is effective and efficient testing of 3D ICs. Just like traditional 2D chips, 3D chips need to be tested for possible manufacturing defects. To minimize any yield loss and reduce overall cost, each die should not only be fully tested before stacking, but also post-stacking re-testing of individual dies is required to confirm that the stacking process did not damage the individual die. In addition, a new kind of test must be performed to check that inter-die interconnects are defects free. Furthermore, the passive silicon interposer needs to be tested in order to not become the bottleneck and the major yield killer in the overall design process. In this paper, we describe some of the innovative solutions developed by TSMC in this direction. The paper highlights complexities and issues related to test architecture development and automation, test flow optimization as well as testing of passive interposer that requires special focus from the EDA industry.