Single-precision LU decomposition based on FPGA compared with CPU

FPGA (field programmable gate array) has become an effective way to accelerate the numerical computing. In this paper, we proposed an architecture for small matrix single-precision LU decomposition based on FPGA and show the resource utilization of this design. We also present a novel structure for block multiply in block LU decomposition for large size matrix. The speed of this novel structure will be faster than implemented in general matrix multiplication in block LU decomposition. Our implementation on a Xilinx Virtex-6 XC6VLX240T can speed 2x compared with floating-point LU with MKL on Core-i3.