On the Impact of Through-Silicon-Via-Induced Stress on 65-nm CMOS Devices

Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm, respectively. Measured change of saturation current (I
_on
) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between -55°C and 125 °C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.