Graphically notated fault modeling and safety analysis in the context of electric and electronic architecture development and functional safety

Although fault tree analysis is well established in the industry and its application is proposed by the international standard for functional safety for road vehicles - ISO 26262 - it is often time intensive to perform. Tool chains are long, the line of action is not straightforward, annotations in data models are complex and traceability is not self-evident. To overcome these inconveniences, this paper presents an approach for graphically notated failure modeling, based on an integrated data model for electric and electronic architectures and rapidly performing of fault tree analysis during concept phase of system design. We demonstrate the utilization of existing concepts in the domain of electric and electronic architecture modeling to enrich existing architectures with concepts of fault tree analysis. Also, we demonstrate the model-based specification of failure models, their relation to modeling artifacts of electric and electronic architectures and the automated processing of failure expressions without the necessity to leave the development environment for electric and electronic architecture modeling. The presented methodology supports closer links between the development of architectures for safety-critical systems and failure analysis by facilitating traceability between failure and system modeling based on a common data structure and well-established modeling approaches.