A self-timed two-stage flexible ALU implementation

SOCs designed for embedded systems are now widely used on embedded multimedia devices. Processors in these devices may need capabilities to support some compound computations, and the most important of all is multiply and accumulate (MAC) operation. Thus DSP processors or special ALUs are designed to accelerate these computations. Besides the computation issue, how to improve the reliability, stability and power efficiency is also very important. It's well-known that asynchronous circuit can be used to address these issues. Thus, in this paper, we propose a dual-rail two-stage flexible ALU to achieve these goals. We also show the delay time for possible operation combinations.