FPGA implementation of LDPC encoder with approximate lower triangular matrix

This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed introduction to the encoding mechanism of the approximate lower triangular LDPC, and completed the implementation and verification of FPGA hardware.