Single event upset tolerance in flip-flop based microprocessor cores

Soft errors due to single event upsets (SEUs) in the flip-flops of a design are of increasing importance in nanometer technology microprocessor cores. In this work, we present a flip-flop oriented soft error detection and correction technique. It exploits a transition detector at the output of the flip-flop for error detection along with an asynchronous local error correction scheme to provide soft error tolerance. Alternatively, a low cost soft error detection scheme is introduced, which shares a transition detector among multiple flip-flops, while error recovery relies on architectural replay. To validate the proposed approach, it has been applied in the design of a 32-bit MIPS microprocessor core using a 90nm CMOS technology.