Compensation of loop delay in a continuous-time Delta Sigma modulator through HRZ DAC feedback

A Continuous-Time Delta-Sigma Modulator is presented for high resolution audio frequency applications with a sampling frequency of 6.5MHz and a signal bandwidth of 10KHz. Traditionally, such architectures suffer from the issue of `loop-delay', which arises due to various non-idealities present in the circuit. The presented design addresses this problem by using Half-Delayed Return-to-Zero feedback signaling, as opposed to the prevalent Non-Return-to-Zero feedback signaling. The integrated circuit was designed and simulated in 250nm CMOS technology. The results show an improvement of 33.3dB in Signal-to Noise Ratio and stable loop output as compared to traditional architectures.