Position-Dependent Bulk Traps and Carrier Compensation in 4H-SiC Bipolar Junction Transistors

The influence of bulk traps in different regions of 4H-SiC bipolar junction transistors (BJTs) is investigated. The investigation is based on experimental results obtained by implanting up to 10
¹¹
cm
^-2
fluences of helium ions in the collector region. The results indicate that implantations, creating point defect concentrations in the range of the doping level, produce a sufficiently high concentration of traps to reduce the carrier concentration in this specific region. These traps degrade the device characteristics and are irrecoverable up to 500°C annealing. The experimental results are qualitatively analyzed by device simulations using a 2D numerical computer-aided design tool (TCAD). Systematic simulations are then performed by introducing traps at different locations in the BJT (i.e., emitter, base, and collector regions). The results indicate that the device performance is highly dependent on the defect concentration in the base region. The defects at different levels inside the collector also influence the device by producing a compensated layer in the material. However, the same concentration of defects (i.e., ~10
¹⁵
cm
^-3
) has less influence in the emitter region.