A Hysteresis-Based D-Flip-Flop Design in 28 nm CMOS for Improved SER Hardness at Low Performance Overhead

A novel D-Flip-Flop design using hysteresis to improve single-event hardness with low performance overhead is presented. Layout-aware sensitive area simulations were used to estimate the improvement in cross-section for the proposed hysteresis DFF (HDFF) vs. a standard DFF. A test chip with the standard DFF, HDFF, and the DICE FF was designed in a 28 nm CMOS process and exposed to alpha, neutron, and heavy-ion beams. The HDFF design shows 14× and 3× improvements in the alpha and neutron SER, respectively, compared with a standard DFF.