A 1.5mW 1MSPS 16bit SAR ADC with high performance

Analog-to-Digital converter (ADC) based on successive approximation (SAR) are limited in their noise performance. Noise sources such as the sampling noise or the comparator noise can only be reduced with increasing the die size or increasing the power consumption. The only way to achieve compatible effective number of bits is to keep the signal range high. 16bit SAR ADCs are therefore typically designed with 0–5V input voltage ranges and therefore use 5V processes since 15 years. Many circuit techniques have been implemented such as [1, 2, 3] to reduce the power consumption, but these ADCs will finally be limited by the digital power dissipation. A novel dual CDAC architecture was developed to overcome these constraints. 5V transistors are only required for analog input and reference switches. The analog circuitry of the ADC can run from a significantly lower supply voltage with all advantages of modern processes. A test chip was implemented with the help of the Bavarian Research Foundation (BFS).