Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture

This paper proposes a composite instruction for path setup and partitioning of a network on chip using segmented buses. The network connects a distributed memory to a coarse grained reconfigurable architecture. The scheme decreases the partitioning and routing instruction in sequencers (S) for the nodes (N) from Nx3 to a single instruction. This reduction in instruction also bear a small performance benefit as less instructions are scheduled onto the network. Furthermore, it is possible to optimizing the system under application specific constraints. A simple use-case with experiments is defined to show for design trade-offs for these optimization decisions.