Compact Implementation of Skein-256 Hash Function on FPGA

In this paper we have presented a low-area design of Skein-256 hash function on Xilinx Virtex-5 FPGA. Skein is one of the 5 finalists of SHA-3 competition. Our implementation is utilizing only 527 slices and shows a throughput of 1.295 Gbps. Comparing our results with the previous published FPGA implementations of Skein-256, our design reports the best TPS of 2.457. High value of TPS shows the efficiency of our design.