The design and implementation of a multiqueue buffer for VLSI communication switches

The micro-architecture and VLSI implementation of a dynamically allocated multiqueue (DAMQ) buffer are presented. Design tradeoffs for the DAMQ buffer's datapath are discussed and a floorplan and the timing of the major functional units are presented. It is shown that in VLSI switches, with buffers than can store multiple packets, additional chip area is better used for the control of DAMQ buffers than for increased buffer space in simpler FIFO buffers.<
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