Reduced complexity single and multiple constant multiplication in floating point precision

This paper addresses the automatic generation and optimization of single and multiple constant multipliers in IEEE 754 floating point precision for FPGAs. It is shown that sharing of partial results in multiplication and exponent addition as well as the handling of special input values can greatly reduce the overall hardware complexity. Two methods are used to reduce the complexity of the integer multiplier block: An existing method using adder arithmetic only and a novel optimization method using a reduced amount of embedded multipliers to compute products with large coefficient values. Superior results are shown compared to previous methods. Using adder arithmetic, a slice reduction of 18% for single and 38% for multiple constant floating point multiplication could be achieved. Using embedded multipliers, nearly half of the multipliers could be saved for multiple constants compared to the conventional approach.