CMOS Phase Frequency Detector and Charge Pump for Wireless Sensor Networks

As the key blocks of PLL (phase locked loop) circuits, PFD (Phase Frequency Detector) is dominated to the precision and stability of system, whereas CP (Charge Pump) offers a wide scale of frequency capture scale and fast locked performance. The structure of PFD using transfer gate dynamic D flip-flops and the structure with a wide input scale error amplifier for CP had been presented to achieve a high performance. In the end, the chip was taped out in the process of TSMC 0.18μm CMOS. The post-simulation results show that the PFD has correct logic function, whereas the charge pump current is stable at 100μA in the output range of 0.2V∼0.8V, and the current mismatch is less than 0.4μA at output voltage range of 0.2V∼0.8V, with total power consumption of 3mW with the power supply of 1V.