Problem of timing mismatch in interleaved ADCs

Time interleaving can relax the speed-power trade-off of analog-to-digital converters but at the cost of sensitivity to interchannel mismatches. This paper addresses the problem of timing mismatch, its detection, and its correction. A new frequency-domain analysis gives insight into the impact of the mismatch on random input signals and quantifies the resulting noise. A number of timing error calibration techniques are reviewed and a new approach is proposed.