A Full-Band processor for reduction of RF mixer LO harmonic images

A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the interference caused by strong blockers that may be inadvertently folded onto the desired channel by local oscillator (LO) harmonics or spurs. This processor digitizes the entire cable or broadcast television spectrum from 50-1000 MHz and can adaptively cancel folded blocker interference from anywhere within this range. An image reduction of at least 23dB was measured. The processor is embedded within an integrated 40nm CMOS DVB-T2 TV receiver including tuner, demodulator and FEC. The complete embedded RF/analog/DSP HRC processor has an area of 0.38 mm
²
and uses 205 mW.