A 7b 1.4GS/s ADC with offset drift suppression techniques for one-time calibration

A 7b 1.4 GS/s flash ADC is developed in 45 nm CMOS. This is the first paper of an ADC with offset drift suppression techniques for dynamic comparator and preamplifier. These techniques make the ADC robust against environmental variation. As a result, once the ADC is calibrated at power up, no more calibration is necessary even under VDD or temperature variations. The ADC occupies a small area of 0.085 mm
²
and dissipates 33.24 mW at 1.4 GS/s from a 1.15V supply.