Low power clock-synchronizer for SOC with delay line controller (DLC) in 45nm CMOS technology

Clock synchronizer is the circuit which synchronizes the clock provided to different loads (modules or functional blocks). The advancement of the VLSI has led to new field- SoC. The clock synchronizer finds its application in SoC. The clock-synchronizer in SoC has to maintain the clock skew between modules zero. This paper presents clock synchronizer architecture. This synchronizer is designed on 45nm CMOS technology, simulated using Tanner EDA tool and T-SPICE, with 2V power supply. The average power consumed is 6.688514e-002 watts.