Leakage current reduction in domino logic

Leakage current reduction has been in the forefront of research for improving domino circuits. By increasing the gate oxide thickness in a previously introduced dual threshold source following evaluation AND gate, an improvement in the leakage characteristics is observed. Also by restructuring the dual threshold SEFG AND gate as an OR gate, the leakage characteristic is enhanced. Remarkably, these modifications have not degraded the delay characteristics. These is due to the fact that the thick oxide transistors are not utilized in the critical paths of the logic circuit and are carefully calibrated -using hspice and BSIM4 45nm models [1]-to only affect leakage.