A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS

In this paper, a novel clock and data recovery scheme for 10Gbps source synchronous receiver is presented in 65nm CMOS technology, which includes the implementation of a quadrature clock generation circuit and a 10Gbps CDR circuit. The quadrature clock generation circuit is based on an open loop delay line, avoiding the design of the complex DLL or PLL loop which is often used in source synchronous links. The 10Gbps CDR is based on phase interpolator, and a novel clock and data recovery algorithm is proposed to reduce jitter of the recovered clock. The power consumption is 25mW under 1.2V power supply.