Rolled architecture based implementation of AES using T-Box

This paper proposes a rolled architecture for the implementation of the 128 bit AES (Advanced Encryption Standard) algorithm. The design comprises of modified T-boxes. The efficient utilization of area and the increase in speed up to 1.454 Gbps is achieved on Xilinx's Virtex-4 Field Programmable Gate Array (FPGA). The clock frequency of the design is 113.63 MHz. By using 24 bit words instead of 32 bits words in T-boxes, memory requirement reduced by 25%. The design employs BRAMs available on the device for T-Boxes and for storing round keys generated in the Key expansion module. The latency achieved is 10 clock cycles and for every new key same amount of clock cycles are required before start of encryption.