Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration

As the two most widely used techniques to reduce dynamic power and leakage power, clock gating (CG) and power gating (PG), respectively, are expected to be integrated together effectively. Normally, the implementation of CG leads to some redundant operations, which provides the opportunity to apply PG. In this brief, we have proposed an activity-driven fine-grained CG and PG integration. First, we introduce an optimized bus-specific-clock-gating (OBSC) scheme to improve traditional XOR-based CG. It chooses only a subset of flip-flops (FFs) to be gated selectively, and the problem of gated FF selection is reduced from exponential complexity into linear. Then those combinational logics, which completely depend on the outputs of gated FFs, are performing redundant operations. They can be power gated, and the clock enable signal generated by OBSC is used as the sleep signal. A minimum average idle time concept is proposed to determine whether the insertion of PG will lead to energy reduction. In order to evaluate our technique, we experimented on twenty ISCAS'89 circuits. The simulation results show that 25.07% dynamic power can be reduced by OBSC, and 50.19% active leakage power can be saved by PG.