A 12b 60MS/s SHA-less opamp-sharing pipeline A/D with switch-embedded dual input OTAs

A 12-bit 60 MS/s SHA-less opamp sharing pipeline ADC utilizing switch-embedded dual-input current-reused opamp is presented in this paper. The proposed opamp sharing technique reduces the power consumption without suffering from memory effect. Two-phase overlapping clocks are proposed to ensure analog transistors in the common-mode feedback (CMFB) loop to always work in saturation thus avoiding common mode voltage settling due to the switch turn-on delay. To further reduce the power consumption, the sampling clock in the first multiplying digital-to-analog converter (MDAC) is split into two phases to reduce the gain-bandwidth (GBW) requirement of the flash ADC without sacrificing the opamp settling time. The ADC fabricated in a 0.13-μm CMOS process demonstrates a maximum SNDR of 64.9 dB and a peak SFDR of 77.1 dB at 60 MS/s. The core ADC with an active die area of 2.3 mm
²
consumes 36 mW of power at 60 MS/s under 1.2-V power supply.