Live demonstration: Hierarchical Address-Event Routing architecture for reconfigurable large scale neuromorphic systems

Recent advances in neuromorphic engineering for brain-like computing and neural prostheses are converging towards realization of electronic synaptic arrays approaching the integration density and energy efficiency of the human brain. A major impediment in this development is the real-time synaptic routing in a large-scale spiking neuron architecture. Here we present a hierarchical address-event routing (HiAER) communication architecture for routing neural events in a scaleable reconfigurable large-scale neuromorphic system. The neural events are routed in real-time through synaptic connections with configurable parameters governing connectivity, synaptic strength, and axonal delay. The HiAER architecture is implemented on a hardware platform with five Xilinx Spartan-6 FPGA cores.