Floorplan-aware hierarchical NoC topology with GALS interfaces

Networks-on-chip has been seen as an interconnect solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors System-on-Chip (MPSoC). Complex router architectures can be prohibitive for the embedded domain, once they dissipate too much power and energy. In this paper we propose a low power hierarchical network topology with GALS interfaces, allowing each cluster operates in a specific frequency. The clusters are composed by crossbar devices and the number of cores allocated for each cluster is defined considering floorplan information. Experimental results show that our strategy can reduce the power dissipation in up to 58% and the latency in up to 56% for the benchmarks analyzed when compared with a packet-switched mesh network-on-chip.